In addition to the usual graph/node/edge data, wiring diagrams allow arbitrary data on input and output ports.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 | input_port_data(g, node, port)
input_port_data(g, node, port) <- value
input_port_attr(g, node, port, key)
input_port_attr(g, node, port, key) <- value
output_port_data(g, node, port)
output_port_data(g, node, port) <- value
output_port_attr(g, node, port, key)
output_port_attr(g, node, port, key) <- value
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