event: Events
In RBigData/pbdPAPI: Programming with Big Data --- Interface to PAPI
Description
Usage
Arguments
Details
Value
Examples
Description
PAPI events.
Usage
1
2
3
papi.avail(events)
ipcm.avail(events)
Arguments
events
A vector of PAPI events (as strings). See details section for
more information.
Details
To determine which counters are available on the target platform, the
papi.avail() function is provided. If no arguments are provided, a
complete list of PAPI events and their availability will be returned.
Otherwise, the list will be limited to the specified events.
There is a physical limitation to the number of counters that any given
analysis may profile, and whence an events counter vector must be no larger
than the total number of hardware counters. You can see how many counters
are available by calling system.ncounters().
The complete list of possible hardware events that one can profile with
pbdPAPI is given below. Note that not all counters will be available on any
given platform.
Cache misses:
"PAPI_L1_DCM" Level 1 data cache misses
"PAPI_L1_ICM" Level 1 instruction cache misses
"PAPI_L1_TCM" Level 1 total cache misses
"PAPI_L2_DCM" Level 2 data cache misses
"PAPI_L2_ICM" Level 2 instruction cache misses
"PAPI_L2_TCM" Level 2 total cache misses
"PAPI_L3_DCM" Level 3 data cache misses
"PAPI_L3_ICM" Level 3 instruction cache misses
"PAPI_L3_TCM" Level 3 total cache misses
Cache hits:
"PAPI_L1_DCH" L1 data Cache Hit
"PAPI_L1_ICH" L1 instruction cache hits
"PAPI_L1_TCH" L1 total cache hits
"PAPI_L2_DCH" L2 data Cache Hit
"PAPI_L2_ICH" L2 instruction cache hits
"PAPI_L2_TCH" L2 total cache hits
"PAPI_L3_DCH" L3 Data Cache Hit
"PAPI_L3_ICH" L3 instruction cache hits
"PAPI_L3_TCH" L3 total cache hits
Cache accesses:
"PAPI_L1_DCA" L1 data Cache Access
"PAPI_L1_ICA" L1 instruction cache accesses
"PAPI_L1_TCA" L1 total cache accesses
"PAPI_L2_DCA" L2 data Cache Access
"PAPI_L2_ICA" L2 instruction cache accesses
"PAPI_L2_TCA" L2 total cache accesses
"PAPI_L3_DCA" L3 data Cache Access
"PAPI_L3_ICA" L3 instruction cache accesses
"PAPI_L3_TCA" L3 total cache accesses
Cache reads:
"PAPI_L1_DCR" L1 data Cache Read
"PAPI_L1_ICR" L1 instruction cache reads
"PAPI_L1_TCR" L1 total cache reads
"PAPI_L2_DCR" L2 data Cache Read
"PAPI_L2_ICR" L2 instruction cache reads
"PAPI_L2_TCR" L2 total cache reads
"PAPI_L3_DCR" L3 data Cache Read
"PAPI_L3_ICR" L3 instruction cache reads
"PAPI_L3_TCR" L3 total cache reads
Cache writes:
"PAPI_L1_DCW" L1 data Cache Write
"PAPI_L1_ICW" L1 instruction cache writes
"PAPI_L1_TCW" L1 total cache writes
"PAPI_L2_DCW" L2 data Cache Write
"PAPI_L2_ICW" L2 instruction cache writes
"PAPI_L2_TCW" L2 total cache writes
"PAPI_L3_DCW" L3 data Cache Write
"PAPI_L3_ICW" L3 instruction cache writes
"PAPI_L3_TCW" L3 total cache writes
Instructions executed:
"PAPI_BR_UCN" Unconditional branch instructions executed
"PAPI_BR_CN" Conditional branch instructions executed
"PAPI_TOT_INS" Total instructions executed
"PAPI_INT_INS" Integer instructions executed
"PAPI_FP_INS" Floating point instructions executed
"PAPI_LD_INS" Load instructions executed
"PAPI_SR_INS" Store instructions executed
"PAPI_BR_INS" Total branch instructions executed
"PAPI_VEC_INS" Vector/SIMD instructions executed
"PAPI_LST_INS" Total load/store instructions executed
"PAPI_SYC_INS" Synchronization instructions executed
Stalls:
"PAPI_MEM_SCY" Cycles Stalled Waiting for Memory Access
"PAPI_MEM_RCY" Cycles Stalled Waiting for Memory Read
"PAPI_MEM_WCY" Cycles Stalled Waiting for Memory Write
"PAPI_RES_STL" Cycles processor is stalled on resource
"PAPI_FP_STAL" FP units are stalled
Cycles:
"PAPI_BRU_IDL" Cycles branch units are idle
"PAPI_FXU_IDL" Cycles integer units are idle
"PAPI_FPU_IDL" Cycles floating point units are idle
"PAPI_LSU_IDL" Cycles load/store units are idle
"PAPI_STL_ICY" Cycles with No Instruction Issue
"PAPI_FUL_ICY" Cycles with Maximum Instruction Issue
"PAPI_STL_CCY" Cycles with No Instruction Completion
"PAPI_FUL_CCY" Cycles with Maximum Instruction Completion
"PAPI_TOT_CYC" Total cycles
"PAPI_CA_SNP" Snoops
"PAPI_CA_SHR" Request for access to shared cache line (SMP)
"PAPI_CA_CLN" Request for access to clean cache line (SMP)
"PAPI_CA_INV" Cache Line Invalidation (SMP)
"PAPI_CA_ITV" Cache Line Intervention (SMP)
"PAPI_TLB_DM" Data translation lookaside buffer misses
"PAPI_TLB_IM" Instruction translation lookaside buffer misses
"PAPI_TLB_TL" Total translation lookaside buffer misses
"PAPI_L1_LDM" Level 1 load misses
"PAPI_L1_STM" Level 1 store misses
"PAPI_L2_LDM" Level 2 load misses
"PAPI_L2_STM" Level 2 store misses
"PAPI_L3_LDM" Level 3 load misses
"PAPI_L3_STM" Level 3 store misses
"PAPI_BTAC_M" BTAC miss
"PAPI_PRF_DM" Prefetch data instruction caused a miss
"PAPI_TLB_SD" Translation lookaside buffer shootdowns (SMP)
"PAPI_CSR_FAL" Failed store conditional instructions
"PAPI_CSR_SUC" Successful store conditional instructions
"PAPI_CSR_TOT" Total store conditional instructions
"PAPI_HW_INT" Hardware interrupts
"PAPI_BR_TKN" Conditional branch instructions taken
"PAPI_BR_NTK" Conditional branch instructions not taken
"PAPI_BR_MSP" Conditional branch instructions mispredicted
"PAPI_BR_PRC" Conditional branch instructions correctly predicted
"PAPI_FMA_INS" FMA instructions completed
"PAPI_TOT_IIS" Total instructions issued
"PAPI_FML_INS" FM ins
"PAPI_FAD_INS" FA ins
"PAPI_FDV_INS" FD ins
"PAPI_FSQ_INS" FSq ins
"PAPI_FNV_INS" Finv ins
If pbdPAPI is built using Intel PCM, pbdPAPI understands only the following
counters. A subset of these will be available depending on your platform.
"IPCM_L2_TCM" Level 2 cache misses
"IPCM_L2_TCH" Level 2 cache hits
"IPCM_INS_RET" Instructions retired
"IPCM_CYC" Cycles used
"IPCM_L3_TCH_NS" Level 3 cache hits without snooping on level 2 cache
"IPCM_L3_TCH_S" Level 3 cache hits with snooping on level 2 cache
"IPCM_L3_TCH" Level 3 cache hits
"IPCM_L3_TCM" Level 3 cache misses
Value
If no argument is specified, then a dataframe detailing all events,
event names, and platform support is returned. If an events vector is
passed, then a logical vector is returned.
Examples
1
2
3
4
5
6
7
8
9
10
11
## Not run:
library(pbdPAPI)
### Check all events
system.avail()
### Check an events vector of events
events <- c("PAPI_L1_DCM", "PAPI_L2_DCM")
system.event(events)
## End(Not run)
RBigData/pbdPAPI documentation built on May 8, 2019, 5:48 a.m.
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Description Usage Arguments Details Value Examples
Description
PAPI events.
Usage
1 2 3 | papi.avail(events)
ipcm.avail(events)
|
Arguments
events |
A vector of PAPI events (as strings). See details section for more information. |
Details
To determine which counters are available on the target platform, the
papi.avail() function is provided. If no arguments are provided, a
complete list of PAPI events and their availability will be returned.
Otherwise, the list will be limited to the specified events.
There is a physical limitation to the number of counters that any given
analysis may profile, and whence an events counter vector must be no larger
than the total number of hardware counters. You can see how many counters
are available by calling system.ncounters().
The complete list of possible hardware events that one can profile with pbdPAPI is given below. Note that not all counters will be available on any given platform.
Cache misses:
| "PAPI_L1_DCM" | Level 1 data cache misses |
| "PAPI_L1_ICM" | Level 1 instruction cache misses |
| "PAPI_L1_TCM" | Level 1 total cache misses |
| "PAPI_L2_DCM" | Level 2 data cache misses |
| "PAPI_L2_ICM" | Level 2 instruction cache misses |
| "PAPI_L2_TCM" | Level 2 total cache misses |
| "PAPI_L3_DCM" | Level 3 data cache misses |
| "PAPI_L3_ICM" | Level 3 instruction cache misses |
| "PAPI_L3_TCM" | Level 3 total cache misses |
Cache hits:
| "PAPI_L1_DCH" | L1 data Cache Hit |
| "PAPI_L1_ICH" | L1 instruction cache hits |
| "PAPI_L1_TCH" | L1 total cache hits |
| "PAPI_L2_DCH" | L2 data Cache Hit |
| "PAPI_L2_ICH" | L2 instruction cache hits |
| "PAPI_L2_TCH" | L2 total cache hits |
| "PAPI_L3_DCH" | L3 Data Cache Hit |
| "PAPI_L3_ICH" | L3 instruction cache hits |
| "PAPI_L3_TCH" | L3 total cache hits |
Cache accesses:
| "PAPI_L1_DCA" | L1 data Cache Access |
| "PAPI_L1_ICA" | L1 instruction cache accesses |
| "PAPI_L1_TCA" | L1 total cache accesses |
| "PAPI_L2_DCA" | L2 data Cache Access |
| "PAPI_L2_ICA" | L2 instruction cache accesses |
| "PAPI_L2_TCA" | L2 total cache accesses |
| "PAPI_L3_DCA" | L3 data Cache Access |
| "PAPI_L3_ICA" | L3 instruction cache accesses |
| "PAPI_L3_TCA" | L3 total cache accesses |
Cache reads:
| "PAPI_L1_DCR" | L1 data Cache Read |
| "PAPI_L1_ICR" | L1 instruction cache reads |
| "PAPI_L1_TCR" | L1 total cache reads |
| "PAPI_L2_DCR" | L2 data Cache Read |
| "PAPI_L2_ICR" | L2 instruction cache reads |
| "PAPI_L2_TCR" | L2 total cache reads |
| "PAPI_L3_DCR" | L3 data Cache Read |
| "PAPI_L3_ICR" | L3 instruction cache reads |
| "PAPI_L3_TCR" | L3 total cache reads |
Cache writes:
| "PAPI_L1_DCW" | L1 data Cache Write |
| "PAPI_L1_ICW" | L1 instruction cache writes |
| "PAPI_L1_TCW" | L1 total cache writes |
| "PAPI_L2_DCW" | L2 data Cache Write |
| "PAPI_L2_ICW" | L2 instruction cache writes |
| "PAPI_L2_TCW" | L2 total cache writes |
| "PAPI_L3_DCW" | L3 data Cache Write |
| "PAPI_L3_ICW" | L3 instruction cache writes |
| "PAPI_L3_TCW" | L3 total cache writes |
Instructions executed:
| "PAPI_BR_UCN" | Unconditional branch instructions executed |
| "PAPI_BR_CN" | Conditional branch instructions executed |
| "PAPI_TOT_INS" | Total instructions executed |
| "PAPI_INT_INS" | Integer instructions executed |
| "PAPI_FP_INS" | Floating point instructions executed |
| "PAPI_LD_INS" | Load instructions executed |
| "PAPI_SR_INS" | Store instructions executed |
| "PAPI_BR_INS" | Total branch instructions executed |
| "PAPI_VEC_INS" | Vector/SIMD instructions executed |
| "PAPI_LST_INS" | Total load/store instructions executed |
| "PAPI_SYC_INS" | Synchronization instructions executed |
Stalls:
| "PAPI_MEM_SCY" | Cycles Stalled Waiting for Memory Access |
| "PAPI_MEM_RCY" | Cycles Stalled Waiting for Memory Read |
| "PAPI_MEM_WCY" | Cycles Stalled Waiting for Memory Write |
| "PAPI_RES_STL" | Cycles processor is stalled on resource |
| "PAPI_FP_STAL" | FP units are stalled |
Cycles:
| "PAPI_BRU_IDL" | Cycles branch units are idle |
| "PAPI_FXU_IDL" | Cycles integer units are idle |
| "PAPI_FPU_IDL" | Cycles floating point units are idle |
| "PAPI_LSU_IDL" | Cycles load/store units are idle |
| "PAPI_STL_ICY" | Cycles with No Instruction Issue |
| "PAPI_FUL_ICY" | Cycles with Maximum Instruction Issue |
| "PAPI_STL_CCY" | Cycles with No Instruction Completion |
| "PAPI_FUL_CCY" | Cycles with Maximum Instruction Completion |
| "PAPI_TOT_CYC" | Total cycles |
| "PAPI_CA_SNP" | Snoops |
| "PAPI_CA_SHR" | Request for access to shared cache line (SMP) |
| "PAPI_CA_CLN" | Request for access to clean cache line (SMP) |
| "PAPI_CA_INV" | Cache Line Invalidation (SMP) |
| "PAPI_CA_ITV" | Cache Line Intervention (SMP) |
| "PAPI_TLB_DM" | Data translation lookaside buffer misses |
| "PAPI_TLB_IM" | Instruction translation lookaside buffer misses |
| "PAPI_TLB_TL" | Total translation lookaside buffer misses |
| "PAPI_L1_LDM" | Level 1 load misses |
| "PAPI_L1_STM" | Level 1 store misses |
| "PAPI_L2_LDM" | Level 2 load misses |
| "PAPI_L2_STM" | Level 2 store misses |
| "PAPI_L3_LDM" | Level 3 load misses |
| "PAPI_L3_STM" | Level 3 store misses |
| "PAPI_BTAC_M" | BTAC miss |
| "PAPI_PRF_DM" | Prefetch data instruction caused a miss |
| "PAPI_TLB_SD" | Translation lookaside buffer shootdowns (SMP) |
| "PAPI_CSR_FAL" | Failed store conditional instructions |
| "PAPI_CSR_SUC" | Successful store conditional instructions |
| "PAPI_CSR_TOT" | Total store conditional instructions |
| "PAPI_HW_INT" | Hardware interrupts |
| "PAPI_BR_TKN" | Conditional branch instructions taken |
| "PAPI_BR_NTK" | Conditional branch instructions not taken |
| "PAPI_BR_MSP" | Conditional branch instructions mispredicted |
| "PAPI_BR_PRC" | Conditional branch instructions correctly predicted |
| "PAPI_FMA_INS" | FMA instructions completed |
| "PAPI_TOT_IIS" | Total instructions issued |
| "PAPI_FML_INS" | FM ins |
| "PAPI_FAD_INS" | FA ins |
| "PAPI_FDV_INS" | FD ins |
| "PAPI_FSQ_INS" | FSq ins |
| "PAPI_FNV_INS" | Finv ins |
If pbdPAPI is built using Intel PCM, pbdPAPI understands only the following counters. A subset of these will be available depending on your platform.
| "IPCM_L2_TCM" | Level 2 cache misses |
| "IPCM_L2_TCH" | Level 2 cache hits |
| "IPCM_INS_RET" | Instructions retired |
| "IPCM_CYC" | Cycles used |
| "IPCM_L3_TCH_NS" | Level 3 cache hits without snooping on level 2 cache |
| "IPCM_L3_TCH_S" | Level 3 cache hits with snooping on level 2 cache |
| "IPCM_L3_TCH" | Level 3 cache hits |
| "IPCM_L3_TCM" | Level 3 cache misses |
Value
If no argument is specified, then a dataframe detailing all events, event names, and platform support is returned. If an events vector is passed, then a logical vector is returned.
Examples
1 2 3 4 5 6 7 8 9 10 11 | ## Not run:
library(pbdPAPI)
### Check all events
system.avail()
### Check an events vector of events
events <- c("PAPI_L1_DCM", "PAPI_L2_DCM")
system.event(events)
## End(Not run)
|
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